Over the next few weeks as time allows, I am going to layout some of the fundamental design variations of next generation "Full Flash (SSD)" Storage arrays. To start off with, it is important to provide an overview of Flash (SSD) and how they work. It the simplest form, there are two type of core flash architecture technology. These are NAND and NOR architectures. I have provided details on both NAND and NOR, but our primary focus will be around NAND (MLC) - Multi Level Cell and (SLC) - Single Level Cell structures.
Flash memory (both NOR and NAND types) were invented by Dr. Fujio Masuoka while working for Toshiba in the 1980's. According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera.
Principles of Operation
Flash memory stores information in an array of memory cells made from floating-gate transistors. In traditional single-level cell (SLC) devices, each cell stores only one bit of information. Some newer flash memory, known as multi-level cell (MLC) devices, including triple-level cell (TLC) devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells. The floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-conductive (as in SONOS flash memory).
Flash Cell Structure
In flash memory, each memory cell resembles a standard MOSFET, except the transistor has two gates instead of one. On top is the control gate (CG), as in other MOS transistors, but below this there is a floating gate (FG) insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, any electrons placed on it are trapped there and, under normal conditions, will not discharge for many years. When the FG holds a charge, it screens (partially cancels) the electric field from the CG, which modifies the threshold voltage (VT) of the cell (more voltage has to be applied to the CG to make the channel conduct). For read-out, a voltage intermediate between the possible threshold voltages is applied to the CG, and the MOSFET channel's conductivity tested (if it's conducting or insulating), which is influenced by the FG. The current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.
In NOR gate flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate: when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR Flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.
NOR Flash Layout
NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors' VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash.
Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only 1 bit at a time. Execute-In-Place applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash.
To read, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagram.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistor below the size where they can be made reliably, to the size where further reductions would increase the number of faults faster than it would increase the total storage available.
NAND Flash Structure
Writing and Erasing
NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today.
Another limitation is that flash memory has a finite number of program-erase cycles (typically written as P/E cycles). Most commercially available flash products are guaranteed to withstand around 100,000+ P/E cycles, before the wear begins to deteriorate the integrity of the storage. Micron Technology and Sun Microsystems announced an SLC NAND flash memory chip rated for 1,000,000 P/E cycles on December 17, 2008.
The guaranteed cycle count may apply only to block zero (as is the case with TSOP NAND devices), or to all blocks (as in NOR). This effect is partially offset in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between sectors; this technique is called wear leveling. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called bad block management (BBM). For portable consumer devices, these wearout management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high reliability data storage, however, it is not advisable to use flash memory that would have to go through a large number of programming cycles. This limitation is meaningless for 'read-only' applications such as thin clients and routers, which are programmed only once or at most a few times during their lifetimes.
Advantages of NAND
Because of the efficient architecture of NAND flash, its cell size is much smaller than a NOR cell. This, in combination with a simpler production process, enables NAND architecture to offer higher densities with more capacity on a given die size. The cost per bit is much lower than NOR. As a result, more bits of NAND memory have been sold than any other type.
NAND is not, however, a perfect memory. As a result of the extremely small scaling and the NAND architecture, it is susceptible to data retention issues and to bits becoming unusable. Because of these imperfections in NAND, complex software needs to be used to administer things like wear-leveling, error correction, and bad block management.
There are different types of NAND devices. Many NAND devices fall in the category of "bare" NAND or "raw" NAND. These devices have all of the issues with wear-leveling, error correction, and bad block schemes.
Another type of NAND device is "managed" NAND, sometimes referred to as embedded flash drives. These devices are NAND stacked with a controller that manages the wear-leveling, error correction codes, and bad blocking schemes. An example of this type of device would be embedded MMC.
Increasing NAND Densities
Because of the increasing need to get higher density devices and lower cost per bit, NAND flash vendors are trying many different strategies. The most common strategies is to use increasingly smaller lithography width and to increase from one bit per cell to multiple bits per cell. As the lithography gets smaller and as the number of bits per cell increases to 2, 3, or 4 bits, the memory density increases correspondingly. However, there are tradeoffs associated with this move related to read/write speeds, data retention, endurance, and error correction complexity. Dealing with these tradeoffs requires increasingly complicated controllers and software methods.
The diagram below shows a comparison of NAND Flash and NOR Flash cells. NAND efficiencies are due in part to the small number of metal contacts in the NAND Flash string. NAND Flash cell size is much smaller than NOR Flash cell size—4F2 compared to 10F2—because NOR Flash cells require a separate metal contact for each cell.
NAND Flash is very similar to a hard-disk drive. It is sector-based (page-based) and well suited for storage of sequential data such as pictures, video, audio, or PC data. Although random access can be accomplished at the system level by shadowing the data to RAM, doing so requires additional RAM storage. Also, like a hard-disk drive, a NAND Flash device may have bad blocks and requires error-correction code (ECC) to maintain data integrity.
NAND Flash cells are 60% smaller than NOR Flash cells, providing the higher densities required for today’s low-cost consumer devices in a significantly reduced die area.
NAND Flash is used in virtually all removable cards, including USB drives, secure digital (SD) cards, memory stick cards, CompactFlash cards, and multimedia cards (MMCs).
The NAND Flash multiplexed interface provides a consistent pinout for all recent devices and densities. This pinout allows designers to use lower densities and migrate to
higher densities without any hardware changes to the printed circuit board.
MLC (Multi Level Cell) and SLC (Single Level Cell) Solid State Drive Levels
Multi-Level Cell is a memory technology that stores bits of information in multiple levels in a cell. Because of this, MLC drives have a higher storage density and the per MB manufacturing cost is less but there is a higher chance of error on the drive. This type of drive is typically used in consumer based products. Single Level Cell only stores bits of information on a single level per cell. This decreases power consumption and allows for faster transfer speeds. This technology is typically reserved for higher end or enterprise memory cards where speed and reliability are more important than cost.
MLC (Multi Level Cell) and SLC (Single Level Cell) Solid State Drive Cell Failure Rate
SLC drives offer consumers the ability to write to every cell on the drive roughly 100,000 times. MLC drives offer up around 10,000 writes per cell before the cells fail. Reading data off of MLC and SLC drives can be done without causing any particular wear and tear but writing to the drive causes the physical strain mentioned.
NAND SLC (Single Level Cell) Flash Architecture Basic Operation
The 2Gb NAND Flash device is organized as 2048 blocks, with 64 pages per block. Each page is 2112 bytes, consisting of a 2048-byte data area and a 64-byte spare area. The spare area is typically used for ECC, wear-leveling, and other software overhead functions, although it is physically the same as the rest of the page. Many NAND Flash devices are offered with either an 8-bit or a 16-bit interface. Host data is connected to the NAND Flash memory via an 8-bit- or 16-bit-wide bidirectional data bus. For 16-bit devices, commands and addresses use the lower 8 bits (7:0). The upper 8 bits of the 16-bit data bus are used only during data-transfer cycles.
2Gb NAND Flash Device Organized as 2048 Blocks
STEC Zeus IOPS SSD (http://www.stec-inc.com/product/zeusram.php)
Zeus IOPS Solid State Drives deliver the performance of 200 HDDs with just one drive. While hard drive access times are measured in milliseconds, access times for Zeus IOPS are in microseconds, enabling a significant increase in random transactional processing. Beginning with the EMC DMX-4, the STEC Zeus Solid State Drive has been used.
What's After Solid State Technology? - 90GB of Data Stored in 1g of Bacteria
Researchers from the Chinese University of Hong Kong have succeeded in demonstrating data storage and encryption with bacteria.
While current electronic data storage methods approach their limits in density, the team achieved unprecedented results with a colony of E.coli. Their technique allows the equivalent of the United States Declaration of Independence to be stored in the DNA of eighteen bacterial cells. Given there are approximately ten million cells in one gram of biological material, the potential for data storage is huge. Furthermore, data can be encrypted using the natural process of site specific genetic recombination: information is scrambled by recombinase genes, whose actions are controlled by a transcription factor.
However, the technique is not yet perfect. Retrieval of data requires a sequencer, and is therefore tedious and expensive. Additionally, toxic DNA is bound to be present within the stored sequences. It is feared that organisms will mutate to remove such sequences, thereby deleting some of the data.
Consequently, the application of this technology is currently restricted to storing copyright information in genetically engineered organisms. Nevertheless, these results are encouraging. A bacterial medium has the potential to be more resilient than electronic methods of data storage. For example, the bacterium Deinococcus radiodurans is extremely radioresistant; the entrusted information would survive even under the electromagnetic pulse and radiation of nuclear fallout.
A Transmission Electron Micrograph Image of Deinococcus Radiodurans - One of the World's Toughest Bacteria
Data Storage in Live Cells
A United States based soda can weighs 15 grams and is contents weigh 355 grams for a total of 370 grams. 355 grams of bacterial cells have the potential to store 31,950 GB / 31.2 TB of data.